The present invention relates to a fabrication technique for use in the manufacture of a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique that is effective when applied to a process of forming a Co (cobalt) silicide layer on the surface of the source and drain of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) that is formed in a silicon substrate.
As a silicide process for the purpose of suppressing spikes of Co silicide, there is a known technique of depositing a Co film and a TiN film (oxidation barrier film) on the surface of the source and drain of a silicon substrate, forming a dicobalt silicide (Co2Si) film by application of a first heat treatment at a temperature less than 400° C., removing the TiN film and an unreacted Co film by wet etching, and forming a cobalt disilicide (CoSi2) film by application of a second heat treatment at a temperature ranging from 700 to 900° C. (refer to Japanese Unexamined Patent Publication No. Hei 11(1999)-283935, U.S. Pat. No. 6,221,764, Japanese Unexamined Patent Publication No. 2000-243726 and U.S. Pat. No. 6,337,272).
[Patent Publication 1]
Japanese Unexamined Patent Publication No. Hei 11(1999)-283935
[Patent Publication 2]
U.S. Pat. No. 6,221,764
[Patent Publication 3]
Japanese Unexamined Patent Publication No. 2000-243726
[Patent Publication 4]
U.S. Pat. No. 6,337,272